Advancement in integrated circuit technology had lead to vast improvements in the speed of integrated circuits, i.e. the time in which the output of a circuit reacts in response to a new input. Increasing integrated circuit speed has resulted in faster rise and fall times of the output voltages. Similarly, the fast rise and fall times of the output voltages have resulted in abrupt transitions of output current.
While faster speeds are very desirable, the abrupt transition of output currents has created serious problems. The package which holds an integrated circuit device has metallic leads which allow interconnection of the device on a circuit board. Each lead has a small inductance associated with it. The leads are connected to the integrated circuit using bonding wire, which also has an inductance associated with it. Voltage is related to inductance and the time rate of change of current by the equation E=L*dI/dT, where L is the measure of inductance, and dI/dT is the change in current with respect to time. The abrupt transition of output currents creates a large change of current at the ground and power supply leads and in the bonding wire, resulting in ground and power supply voltage spikes. These voltage spikes affect the output voltages of the device, and cause output ringing, ground bounce, and false signals.
Techniques have been heretofore developed which attempt to alleviate this problem by reducing the amount of inductance present in the leads. One method provides multiple power supply and ground leads in order to reduce the inductance (L) that generates the voltage spikes. However, the reduction in inductance is often insufficient to eliminate voltage spikes at the output of many devices, and may necessitate using a larger package to carry the same integrated circuit.
Another method has attempted to reduce the effects of the voltage spikes by bifurcating the surge of current through the lead inductances of the package. The large pull-down transistor in the standard CMOS buffer is split into two devices separated by a resistor. The resistor delays the turn-on of the second device so that the circuit produces two smaller current spikes rather than one large current spike. While somewhat slowing the edge of the output current transition, this circuit is often insufficient to bring the dI/dT term to a value which will reduce voltage spikes at the power and ground leads.
In the integrated circuit devices shown in the previously mentioned related applications, a substrate has a plurality of semiconductor areas forming the sources and drains of a plurality of transistor regions. A continuous serpentine gate, typically made of polysilicon, extends from one to another of these regions to provide the gate conductor of each. This serpentine gate has a predetermined resistance. A signal applied to a first end region of the gate propagates along the length of the gate during a predetermined time interval. As this signal propagates along the gate, it turns on the transistor regions in sequence. As a result, the single distributed transistor which is comprised of the plurality of transistor regions, turns on incrementally thereby limiting the rate of change of output current with respect to time. Various structures are disclosed for causing a temporary voltage drop along the continuous gate to further limit the rate of change of the output current with respect to time. While the described structures have proven to be very useful in certain applications, there are cases where the amount of delay available with typical polysilicon continuous gates is not sufficient to adequately limit noise resulting from rapid change of current. This is particularly the case with large scale integration (LSI) applications.
From the foregoing, it may be seen that a need has arisen for a technique which produces a smooth change of output current with respect to time in response to switching output voltage states, in order to reduce or eliminate voltage spikes. Furthermore, a need has arisen for circuitry capable of protecting against false outputs without substantially increasing the number of devices needed to implement the circuitry.